Bern RTOS: RTOS Analysis and Rust Introduction

Target Hardware

CPUs in computers predominantly implement the x86_64 architecture. The landscape is different on microcontrollers: there are architectures a manufacturer developed (MSP430, AVR, PIC) and nowadays more common licensed architectures (e.g. ARM Cortex-A/M/R, RISC-V). To run an RTOS kernel on all these cores, architecture specific code must be abstracted. Although the Bern RTOS will not support every architecture, the kernel will be written platform agnostic from the start.

For the Bern RTOS I will focus on ARMv7-M (Cortex-M3) and ARMv7E-M (Cortex-M4) architecture, because they are nearly identical and used in most microcontrollers. If possible, ARMv6-M (Cortex-M0+) will be supported as well. This core is used for low power systems or as application processor in wireless SoCs. For simulation purposes a POSIX implementation would be nice.

Some modern microcontrollers have multiple instances of a CPU core (symmetric multiprocessing, SMP) or cores of different architecture (asymmetric multiprocessing, AMP). Multiprocessing has a significant influence on kernel design, but for now I will focus on single core microcontroller.